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Guild: wafer.space Community
Channel: ℹ️ - Information / general / PEX for taps
After: 2026-06-30 11:59 p.m.
Before: 2026-08-01 12:00 a.m.
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[2026-07-17 7:17 a.m.] 246tnt



[2026-07-17 7:17 a.m.] 246tnt
I'm not sure it will change anything at all.


[2026-07-17 7:20 a.m.] osvel
Yeah right, I think namibj told me earlier that the substrate is not really simulated properly.


[2026-07-17 7:22 a.m.] osvel
I've drawn my tap cells like those generated in klayout (on one side, made of psd/psc) but I feel like I don't really know what I am doing and hoping that simulations can later spot my issues.


[2026-07-17 7:23 a.m.] 246tnt
I wouldn't count on it.


[2026-07-17 7:23 a.m.] 246tnt
But wether that matters or not depends a lot of what you're doing.


[2026-07-17 7:25 a.m.] 246tnt
My understanding is it's mostly about tiny noise and cross talk between circuits, catching stray substrate currents. If you're circuit isn't super low noise or that sensitive, should be just fine


[2026-07-17 7:25 a.m.] 246tnt
Just my 2 ct.


[2026-07-17 7:32 a.m.] osvel
Appreciate all cents i can get 🙂 I'm fine with a bit of noise. Its mostly latch-up I want to be sure I avoid, but maybe its not such a large problem. I have been browsing some designs and I think my method is fine.


[2026-07-17 7:39 a.m.] 246tnt
Latchup you should be fine. The DRC will check there are enough taps and if there are wired to the proper rail it's all good.


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Exported 10 message(s)
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